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TPS23757
www.ti.com
50 mA/div
I PI
Inrush
Cvtr. Starts
SLVS948D – JULY 2009 – REVISED NOVEMBER 2013
V VDD VSS
Detect
Class
-V
V RTN VSS
10 V/div
(Four Point)
-V
t - Time - 50 ms/div
Figure 20. Startup
Detection
The TPS23757 drives DEN to V SS whenever V VDD -V VSS is in the detection state per Figure 19 . When the input
voltage rises above V CL-ON , the DEN pin goes to an open-drain condition to conserve power. While in detection,
RTN is high impedance, and almost all the internal circuits are disabled. An R DEN of 24.9 k ? (1%), presents the
correct signature. It may be a small, low-power resistor since it only sees a stress of about 5 mW. A valid PD
detection signature is an incremental resistance ( Δ V / Δ I ) between 23.7 k ? and 26.3 k ? at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the
parallel combination of R DEN and internal V DD loading. The input diode bridge’s incremental resistance may be
hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is
partially cancelled by the TPS23757's effective resistance during detection.
Detection is the same for type 1 and type 2 PDs.
Hardware Classification
Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with
power management once power is applied. The PSE applies a voltage of between 14.5 V and 20.5 V at the PD
PI and the PD responds with a current representing the class per the standard. A type 1 PD presents class 0 - 3
in hardware to indicate it is a low-power device (no change from IEEE 802.3-2008). Type 1 PD hardware class
interoperates properly with type 2 PSEs. A type 1 PD must present the hardware class which covers its
maximum power draw. IEEE 802.3at provides a new option for type 1 PDs to negotiate their power allocation to
a lower level using DLL after startup. DLL communication is implemented by the ethernet communication system
in the PD and is not implemented by the TPS23757.
The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a
PD if it draws more than its stated class power, which may be the hardware class or an optional lower DLL-
derived power level. The standard permits the PD to draw limited current peaks that increase the instantaneous
power above the Table 1 limit, however the average power requirement always applies.
The TPS23757 disables classification above V CU_OFF to avoid excessive power dissipation. CLS is turned off
during PD thermal limit or when APD, PPD (level 1), or DEN are active. CLS is enabled when APD and PPD
(level 2) are active. The CLS output is inherently current limited, but should not be shorted to V SS for long periods
of time.
Copyright ? 2009–2013, Texas Instruments Incorporated
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